1. Field of the Invention
The invention generally relates to memory access.
2. Description of the Related Art
FIG. 1 illustrates prior art circuitry 100 for a dynamic random access memory (DRAM) architecture. As illustrated in FIG. 1, a memory bank 120 comprises a plurality of memory arrays, such as a memory array 122 for example, each having a plurality of rows of memory cells.
To access one or more memory cells in memory bank 120 at a desired memory address 101 for a read or write command, a row decoder 112 decodes a row address portion 102 of memory address 101 to select and activate one row 132 of memory cells in memory bank 120 by activating a word line to activate switches to couple memory cells in row 132 to corresponding primary sense amplifiers in a sense amplifier bank 162 for row 132. A column decoder 114 decodes a column address portion 104 of memory address 101 to select one column 142 of memory cells by activating switches to couple primary sense amplifiers corresponding to memory cells in column 142 to corresponding local data line pairs, thereby coupling the primary sense amplifier coupled to a memory cell 150 common to row 132 and column 142 to local data line pair 172.
Each sense amplifier bank in memory bank 120 comprises circuitry responsive to the activation of a row of memory cells corresponding to the sense amplifier bank to generate a row valid signal to activate master data line switches corresponding to the sense amplifier bank. The activated master data line switches couple local data line pairs corresponding to the sense amplifier bank to a master data line pair 180 for access to a memory cell in the activated row and a selected column. Sense amplifier bank 162, for example, comprises circuitry responsive to the activation of row 132 to generate a row valid signal to activate master data line switches 182 and therefore couple local data line pair 172 to master data line pair 180 for access, for example, to memory cell 150 when column 142 is selected. Master data line pair 180 leads to a secondary sense amplifier.
Although activating a new row of memory cells is a relatively slow operation due to the amount of time required for precharging and sensing, selecting a new column in an already activated row is a relatively fast operation. Multiple memory cells in an already activated row may therefore be rapidly accessed successively for a single read or write command to improve data throughput. After memory cell 150, for example, has been accessed, a column address counter 119 may be used to access one or more additional memory cells in row 132 successively while row 132 remains activated. Accessing multiple memory cells for a single read or write command is known as a burst access. The number of memory cells to be accessed in a burst access is known as the burst length. The memory cells available for a burst access are known as a page. The number of memory cells available for a burst access is known as the page length.
A single burst access of memory bank 120 is limited, however, to use of only the memory cells in a single activated row. While the number of memory cells in a row may be increased to increase the page length, doing so incurs increased word line resistance and increased access times. Successively accessing large amounts of data, such as for graphics applications for example, therefore requires multiple burst accesses to access multiple rows in memory bank 120. Successively activating multiple rows for access, however, incurs increased latency costs.